This invention relates to passivation of circuit components, and in particular to passivation of metal contacts formed as a part of said circuits.
The need for passivation of circuits, and in particular silicon integrated circuits and devices, has long been recognized. The usual approach is to house the circuit or device in an hermetic package. While effective in protecting the components from moisture and contaminants in the air, this method is expensive. An alternative approach is to cover the components with a layer of silicon nitride or a dual layer of silicon nitride and silicon dioxide. The purpose of such layer or layers is to provide the necessary protection from the ambient without the need for hermetic packaging. The silicon nitride layer can be deposited so that it is essentially crack-free. However, during subsequent processing such as window opening, bonding and wafer separation, cracks develop in the layer which propagate to the metal contacts on the surface of the semiconductor. Since the metal, which is typically aluminum, is susceptible to moisture in the air, such cracking results in poor circuit reliability and low yields. If a layer of SiO.sub.2 is interposed between the metal and silicon nitride, the cracks will propagate through both layers and the same adverse effects are observed.
It is therefore a primary object of the invention to provide for passivation of circuits so that cracking of the passivation layer is minimized, and any cracking which does occur will not have a significant effect on the circuit components.